Applicant's invention relates to a signal-receiving and signal-processing unit comprising a signal-receiving circuit and a signal-processing circuit.
The invention relates more specifically to a signal-receiving circuit and a signal-processing circuit for signals that are pulse-shaped voltage variations having a selected repetition frequency on the order of more than one megabit per second (1 Mb/s), preferably more than 100 Mb/s. The voltage variations are controlled to represent a digital-information-carrying signal, with an internal structure, by a transmitting circuit. The digital signal is distorted by, among other things, the signal-transferring conductor, and the receiving circuit is intended to be able to detect and receive a thus distorted digital signal.
Units of this kind are used to adapt received (distorted) signals into transmitted signals of an internal signal structure. The method is based on adapting a received signal, which presents a somewhat erroneous voltage level and/or is not adapted to a certain common mode (CM) area, by the signal-processing unit, to an internal signal structure more suitable to requirements needed in an exchange of signals.
Such signal-receiving and signal-processing units are connected to a conductor adapted to transmit information-carrying signals in the form of voltage pulses. The conductor is connected to a transistor belonging to a signal-receiving circuit to affect a current by using variations in the voltage pulses and the voltage value of a pulse. The current is in the form of pulses that pass through the transistor, and the current is generated by the voltage pulse variations and voltage level. A signal-processing circuit gives the current a signal-adapted information-carrying form that is better adapted to a certain form of circuit-internal information-carrying signals than was the form of the received signal.
Signal-receiving and signal-processing units of this kind have been useful to evaluate the information content in voltage pulses having a pulse rate in the range of up to 200 Mb/s. Signal-receiving and signal-processing units of this kind have been adapted to detect pulse-shaped voltage variations appearing on a single conductor (single-ended signalling), or to detect pulse-shaped voltage variations appearing on or between two conductors (differential signalling).
For simplification, the following description is limited to only differential signalling, but the invention provides for signal-receiving and signal-processing units for both signalling systems. A person skilled in the art will recognize the measures needed to keep the voltage potential of one conductor at a constant level, which is required for single ended signalling. This will, nevertheless, be described below.
It is further known to use various techniques to manufacture these signal-receiving and signal-processing units to thereby achieve various working conditions for the units. It is known to use both CMOS technology and bipolar technology to manufacture signal-receiving units and signal-processing units of the kind described above. For simplicity, the following description will mainly describe the use of CMOS technology. The differences in function obtained using bipolar technology are of minor significance and would be apparent to a person skilled in the art. Also, the changes required to adapt the CMOS technology and/or the bipolar technology to other known technologies would be apparent to a person skilled in the art.
On manufacturing units of this kind, two criteria, among other things, are significant: (1) the CM area of the signal-receiving circuit and the signal-processing circuit (in a differential signalling system, the CM area is the voltage range within which the received voltage pulses must be for detection by the signal-receiving circuit); and (2) the limiting value of the repetition frequency of the individual voltage variations on the conductors that can be detected and distinguished by the signal-receiving circuit and thereafter processed by the signal-processing circuit.
It is known to connect each of the information-carrying signals that appear on the conductors to a respective gate terminal, the gate terminals belonging to respective PMOS transistors. The CM area would then be the voltage range from somewhat more than half of the supply voltage (Vcc) down to zero potential (see FIG. 3). The use of a PMOS transistor and a post-connected current mirror circuit, such as a post-connected cascode circuit or the like (described below), provides a CM area that is extended downwards to somewhat less than zero potential (approximately -0.7 volt).
It is also known that PMOS transistors provide a lower limiting value of the repetition frequency (up to 200 Mb/s) than provided by an NMOS transistor.
One can also notice that changing the PMOS transistors to NMOS transistors (see FIGS. 3 and 4) would provide a CM area extending from the supply voltage down to somewhat less than half the supply voltage. This is not acceptable since, in a practical application, the CM area has to be at least within the area provided by PMOS transistors and a post-connected current mirror, e.g., a cascode circuit.
It can further be mentioned that when constructing signal-receiving and signal-processing units of this kind it is known to use and coordinate two transistors in the signal-processing circuit (FIG. 3) so that a current through a first one of the transistors is mirrored to be the same as a current through the other transistor. Conditions are thus created that permit the drain-source voltage of the second transistor to vary relatively greatly in relation to the current variation through the first transistor. Such a signal-processing current mirror circuit is described in more detail below with reference to FIG. 1.
To complete this description of known art and to mention a circuit that in some cases can be suitable for the present invention, it should be mentioned that the current through the second transistor can be made independent of the drain-source voltage by using a cascode circuit (a high impedance current generator). Such a cascode circuit, having four transistors, is described in more detail below with reference to FIG. 2.
Other current mirror circuits are also known, such as circuits that use three transistors like the Wilson current mirror. The expression "current mirror circuit" will in the following description and claims be understood to cover every kind of current mirror, regardless of whether two, three, or more transistors are used. The Wilson current mirror and the cascode circuit are current mirror circuits that provide better attributes when connected as current generators.
The publication, "CMOS analog circuit design" by P. E. Allen (ISBN 0-03-006587-9), and German patent document no. DE 35 25 522 provide further and more detailed understanding of the known art.
CMOS technology uses PMOS transistors and NMOS transistors, and in the following every selected transistor will be described with an "N" or a "P" before the respective reference numeral to indicate whether the transistor is an NMOS or PMOS transistor. The following description only mentions NMOS transistors, but that expression is intended to include also bipolar NPN transistors and equivalent transistors of other technologies. Similarly, bipolar PNP transistors and the like will be understood to be included in the expression "PMOS transistors".
Considering the known art as described above and trends in this technical field, it is a technical problem to provide a signal-receiving unit that can at least present a CM area corresponding to that which can be achieved with PMOS transistors, with post-connected current mirror circuits, according to the embodiment in FIG. 4, and that can increase the repetition frequency towards the limit available with fast transistors such as NMOS transistors, bipolar NPN transistors or the like.
It is a technical problem to provide a specific connection of the NMOS transistors in the signal-receiving circuit so that a CM area is provided that comprises voltage variations even below the zero level.
It is also a technical problem to realize the advantages that are achieved by connecting pair-wise related NMOS transistors in the signal-receiving circuit as a current mirror circuit.
It is a further technical problem to realize the advantages that come from letting at least two of the pair-wise connected NMOS transistors be connected together to at least one of the conductors where the voltage pulses appear by their source terminals (or their drain terminals).
It is a technical problem to realize that at a connection of the above-described NMOS transistors the two connected NMOS transistors are connected to each other and to a reference potential by their gate terminals.
It is also a technical problem to compensate, with simple means, time deviations depending on the difference that can appear with transmission systems where a current value, belonging to one of the conductors, is to be mirrored a selected number of times (e.g., n) in the signal-processing circuit, while another current value belonging to the other conductor is to be mirrored another selected number of times (e.g., n+1) before these two current values are to activate an inverter and/or an amplifier or the like.
It is a further technical problem to create a signal-processing unit from NMOS transistors that not only provides a large CM area, from somewhat below zero-level (say, -0.7 volt) up to somewhat more then half the selected supply voltage, for the received signals carrying information as voltage pulses, but that also converts a received voltage pulse into a desired internal signal structure, such as an adaptation to CMOS signals or emitter-coupled-logic (ECL) signals.
It is also a technical problem to create a signal-receiving unit able to detect signals carrying information in the form of voltage pulses with a very high bit rate, in the gigabit per second (Gb/s) range, by at least letting the signal-receiving circuit contain NMOS transistors forming a specific circuit.
It is also a technical problem to realize the importance of letting such NMOS transistors be connected to a first conductor and letting two or several other NMOS transistors be connected to a second conductor to simultaneously be able to receive voltage pulses (voltage values) that are appear on the conductors and convert these to corresponding current values.
It is also a technical problem to realize the importance of letting two pair-wise related NMOS transistors be connected to one and the same conductor and thereby realize that the conductor is to be connected directly to the source or drain terminals of the transistors, if CMOS technology is used, or to the emitter terminals of the transistors, if bipolar technology is used.
It is also a technical problem to realize the importance of letting two NMOS transistors, or bipolar transistors, be mutually connected to a conductor and further to be connected with a number of post-connected current mirror circuits.
It is also a technical problem to realize the importance of a selected number of pair-wise related transistors, for both of the two conductors, being coordinated into current mirror circuits.
It is also a technical problem to use the connections of the pair-wise transistors, one pair from each of the respective two conductors, so that these serve as double floating current mirror circuits.
It is further a technical problem to realize the importance of letting the pair-wise related NMOS transistors be mutually supplied with a current by a cascode circuit or the like.
It is further a technical problem to realize the importance of letting the transistor or transistors be post-connected by pair-wise related current mirror circuits belonging to the signal-processing circuit.
It is further a technical problem to realize the importance of letting a unit belonging to the signal-processing unit that is adapted to evaluate current differences be post-connected by an inverter to generate an output signal.
It should also be regarded as a technical problem to realize the importance of letting one or several current mirror circuits be cascode-connected or the like.